module top(input clk_slow,
           input clk_fast,
           input rst_n,
           input signal_in,
           output signal_out);
    reg signal_a;
    reg signal_a_r;
    reg signal_a_rr;
    reg signal_b;
    reg signal_b_r;
    reg signal_b_rr;
    always @(posedge clk_fast or negedge rst_n)
    begin
        if (!rst_n)
            signal_a <= 1'b0;
        else if (signal_in == 1'b1)
            signal_a <= 1'b1;
        else if (signal_a_rr == 1'b1)
            signal_a <= 1'b0;
        else
            signal_a <= signal_a;
    end
    
    always @(posedge clk_slow or negedge rst_n)
    begin
        if (!rst_n)
            {signal_b_rr, signal_b_r, signal_b} <= {3{1'b0}};
        else
            {signal_b_rr,signal_b_r,signal_b} <= {signal_b_r,signal_b,signal_a};
    end
    
    assign signal_out = signal_b_r&(~signal_b_rr);
    
    always @(posedge clk_fast or negedge rst_n)
    begin
        if (!rst_n)
            {signal_a_rr.signal_a_r} <= {2{1'b0}};
        else
            {signal_a_rr,signal_a_r} <= {signal_a_r,signal_b_r};
    end
    
endmodule
